FPGA驱动LCD显示中文字符“年”程序
--文件名:lcd_driver.vhd。
--功能:FGAD驱动LCD显示中文字符“年”。
--最后修改日期:2004.3.24。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd_driver is
Port ( clk : in std_logic; --状态机时钟信号,同时也是液晶时钟信号,其周期应该满足液晶数据的建立时间
reset:in std_logic;
lcdda : out std_logic; --寄存器选择信号
lcdrw : out std_logic; --液晶读写信号
lcden : out std_logic; --液晶时钟信号
data : out std_logic_vector(7 downto 0)); --液晶数据信号
end lcd_driver;
architecture Behavioral of lcd_driver is
type state is (set_dlnf,set_cursor,set_dcb,set _cgram,write _cgram,set_ddram,write_data);
signal current_state:state;
type ram2 is array(0 to 7) of std_logic_vector(7 downto 0);
constant cgram:ram2:=(("00001000"),("00001111"),("00010010"),
("00001111"),("00001010"),("00011111"),("00000010"),("00000010"));--年字符数据存储器
signal clkk : std_logic;
begin
lcden <= clk ; --液晶时钟信号
lcdrw <= '0' ; --写数据
control:process(clk,reset,current_state) --液晶驱动控制器
variable cnt1: std_logic_vector(2 downto 0);
begin
if reset='0'then
current_state<=set_dlnf;
cnt1:=(others => '1');
lcdda<='0';
elsif rising_edge(clk)then
current_state <= current_state ;
lcdda <= '0';
case current_state is
when set_dlnf=>
data<="00111100";--3cH
current_state<=set_cursor;
when set_cursor=>
data<="00000110";--06H
current_state<=set_dcb;
when set_dcb=>
data<="00001111";--0fH
current_state<=set_ cgram;
when set_ cgram=>
data<="01000000";--40H
current_state<=write_ cgram;
when write_ cgram=> --向CGRAM中写入“年”
lcdda<='1';
cnt1:=cnt1+1;
data<=cgram(conv_integer(cnt1));
if cnt1 = "111" then
current_state<=set_ddram;
end if;
when set_ddram=> --从第一行的起始地址开始显示
data<="10000000";--80H
current_state<=write_data;
when write_data=>
lcdda<='1';
data<="00000000"; --写入字符“年”
when others => null;
end case;
end if;
end process;
end Behavioral;
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MFSK is
port(clk :in std_logic; --系统时钟
start :in std_logic; --开始调制信号
x :in std_logic; --基带信号
y :out std_logic); --调制信号
end MFSK;
architecture behav of MFSK is
process(clk) process(clk,yy) --此进程完成对输入基带信号x的MFSK调制
begin
if clk'event and clk='1' then
if start='0' then y<='0'; -- if语句完成2位并行码到4种载波的选通
elsif yy="00" then y<=not f(3);
elsif yy="01" then y<=not f(2);
elsif yy="10" then y<=not f(1);
else y<=not f(0);
end if;
end if;
end process;
end behav;
--对输入的基带信号x进行串/并转换,得到2位并行信号的yy
begin
if clk'event and clk='1' then
if start='0' then q<=0;
elsif q=0 then q<=1;xx(1)<=x;yy<=xx;
elsif q=8 then q<=9;xx(0)<=x;
else q<=q+1;
end if;
end if;
end process;
FPGA驱动LED静态显示
--文件名:decoder.vhd
--功能:译码输出模块,LED为共阳接法
--最后修改日期:2004.3.24
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port (seg:in std_logic_vector(3 downto 0 ); --四位二进制码输入
q3:out std_logic_vector(6 downto 0) ); --输出LED七段码
end decoder;
architecture Behavioral of decoder is
begin
process(seg)
begin
case seg is
when "0000" => q3<="0000001";--0
when "0001" => q3<="1001111";--1
when "0010" => q3<="0010010";--2
when "0011" => q3<="0000110";--3
when "0100" => q3<="1001100" --4
when "0101" => q3<="0100100";--5
when "0110" => q3<="0100000";--6
when "0111" => q3<="0001111";--7
when "1000" => q3<="0000000";--8
when "1001" => q3<="0000100";--9
when others => q3<="1111111";
end case;
end process;
end Behavioral;
例2:FPGA驱动LED动态显示(4位)
--文件名:dynamic.vhd。
--功能:动态扫描模块,位选信号高电平有效。
--最后修改日期:2004.3.24。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dynamic is
Port ( clk : in std_logic;
reset: in std_logic;
din1 : in std_logic_vector(6 downto 0); --译码后的数据信号1(4位2进制数据
通过例1中的decoder模块译码得到din1,din2,din3,din4)
din2 : in std_logic_vector(6 downto 0); --译码后的数据信号2
din3 : in std_logic_vector(6 downto 0); --译码后的数据信号3
din4 : in std_logic_vector(6 downto 0); --译码后的数据信号4
shift: out std_logic_vector(3 downto 0); --位选信号
bus4 : out std_logic_vector(6 downto 0)); --数据信号
end dynamic;
architecture Behavioral of dynamic is
signal scan_clk:std_logic_vector(1 downto 0);
begin
process(clk,scan_clk,reset) --分频进程
variable scan:std_logic_vector(17 downto 0);
begin
if reset='1' then
scan:="000000000000000000";
scan_clk<="00";
elsif clk'event and clk='1'then
scan:=scan+1;
end if;
scan_clk<=scan(17 downto 16);
end process;
process(scan_clk,din1,din2,din3,din4) --扫描进程
begin
case scan_clk is
when "00"=>
bus4<=din1;
shift<="0001";
when "01"=>
bus4<=din2;
shift<="0010";
when "10"=>
bus4<=din3;
shift<="0100";
when "11"=>
bus4<=din4;
shift<="1000";
when others=> bus4<="0000000";shift<="0000";
end case;
end process;
end Behavioral;
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